1. Field of the Invention
The present invention relates to the fabrication of integrated circuits having trenches, and particularly, to the filling of trenches, forming of a barrier layer, and planarizing a surface over the trenches.
2. Description of Related Art
The incorporation of multiple electrical devices on a single semiconductor wafer resulted in the advent of integrated circuit ("IC") technology. The fabrication of electrically isolated devices is critical in integrated circuit technology. The importance of effective isolation while allowing good surface planarity and occupying minimal space cannot be overemphasized.
In light of the need to isolate the electrical devices, various isolation technologies have been developed. An earlier method termed LOCOS (LOCal Oxidation of Silicon) was developed for p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) IC's to prevent the establishment of parasitic channels between adjacent devices thus providing inter-device isolation. LOCOS isolation involves the formation of a semirecessed oxide in the nonactive (or field) areas of the semiconductor substrate. Eventually, bipolar IC's employed a similar LOCOS isolation technology. However, well-known limitations are associated with LOCOS isolation such as the formation of bird's beak and non-planar surface topography. As device geometries reached submicron size, conventional LOCOS isolation technologies attained the limit of their effectiveness, and alternative isolation technologies were developed to increase the packing density of IC's. One such isolation technology developed involves a process of creating trench structures during IC fabrication. The utilization of trench structures to form electrical isolation areas accomplished several major goals including (1) isolation of transistors in bipolar circuits; (2) prevention of latchup and isolation of n-channel from p-channel devices in complimentary metal oxide semiconductor (CMOS); and (3) usage as storage-capacitor structures in Random Access Memories.
The trench lining, filling, and planarization processes are important factors in the fabrication of desirable trench structures. For example, Rogers et al., U.S. Pat. No. 4,656,497 describes a process of forming an isolation-trench in silicon, lining the trench walls, and filling the trench with silicon dioxide doped with impurities such as boron or phosphorus ("glass"). In order to avoid the presence of voids within the trench fill material and to form a planar surface, the glass is reflowed at atmospheric pressure and elevated temperatures of about 950.degree. C. to 1,150.degree. C. for about 30 minutes to four hours depending upon the glass thickness and the trench dimensions. Subsequently, the trench structure is again subjected to elevated temperatures of about 1,000.degree. C. to 1,200.degree. C. to outgas the phosphorus or boron impurities.
Another example, Lee et al., U.S. Pat. No. 4,952,524 describes a process of forming an isolation trench in a silicon wafer, lining the trench walls, and also filling the trench with an oxide filler material deposited on a thermal stress-relief layer of oxide. Subsequently, the trench fill material is flowed to remove voids and form a planar surface at atmospheric pressure at an elevated temperature preferably higher than the temperatures of all subsequent furnace heat treatments to which the wafer will be subjected.
However, the trenches have contacts between layers of silicon and silicon dioxide. Because of the differing thermal coefficients of expansion of silicon and silicon dioxide and the subjection of the trench structure to the elevated temperatures for relatively long periods of time, stress from the mismatch occurs. This stress tends to cause undesirable damage in silicon areas near the trench. Particularly, top edges of the trenches are susceptible to the generation of stress defects. Additionally, the wafers often contain relatively defined regions of dopant concentrations for active devices prior to the creation of a trench(es). As a result, subjecting the wafer to elevated temperatures for relatively long periods of time can result in the undesirable movement of the dopants outside of the defined regions. Dopant redistribution requires an increase in minimum device separation which in turn decreases device density.
Polysilicon filled trenches are an alternative to oxide filled trenches i.e. after the formation of the trench and lining the trench walls, the trench is filled with polysilicon. However, surface planarity is generally achieved by etching back the polysilicon, capping the structure using LOCOS techniques, and then etching back the LOCOS. Therefore, a very complex combination of multiple process steps is required to achieve surface planarity. Additionally, a diffusion/oxidation barrier such as silicon nitride is often used to line a trench prior to filling of the trench. The LOCOS technique tends to generate a vertical bird's beak in the area lying between the silicon wafer and the barrier layer. The vertical bird's beak will generate undesirable stress defects at the top edges of the trench.